IEEE MVL-TC Bulletin

VOLUME 19 Number 1 March 1998

1. Chair's Message

This is my first message as chair of the MVL-TC. I feel honored to serve in this capacity. I like to thank the past chair, Prof. Michitaka Kameyama, for a job well done. Please send me suggestions on how to make the technical committee more effective.

ISMVL is the premier event in the MVL community, and its date is drawing closer. I like to invite every MVL researcher to come to Fukuoka to participate in this event. This year's program committee has put together a very attractive program. There will be 6 invited presentations with topics ranging from several aspects of hardware to algebra and fuzzy logic.
Details about ISMVL-98 are available elsewhere in this bulletin. Prof. Sasao has set up an excellent web site that contains all information regarding this year's symposium (and even about past symposia). Here is its address http://www2b.meshnet.or.jp/~taku/sasao/ismvl98/. It has been a
tradition to host the Workshop on Post-Binary Ultra-large-Scale Integration Systems in conjunction with ISMVL. This year is no exception, the workshop will be held on May 26, 1998. Please plan to arrive early and participate in this event. Registration is free and the program looks very promising.

I am looking forward to see you in Fukuoka in May.

Gerhard Dueck

2. IEEE MVL Technical Committee Member List

Chair:

Gerhard Dueck (1998-1999)
Dept. of Math., Stats. and Comp. Sci.
St. Francis Xavier University
Antigonish, Nova Scotia
B2G 2W5, CANADA
Phone: (902) 867 2376
Fax: (902) 867 2448
Email: gdueck{at}stfx.ca

Vice Chair:

Takahiro Hanyu (1998-1999)
Graduate School of Information Sci.
Tohoku University
Sendai 980-77
Japan
Phone: +81-22-217-7153
Fax: +81-22-263-9401
Email: hanyu{at}kameyama.ecei.tohoku.ac.jp

Executive Committee:

Chair: Gerhard Dueck

Vice-Chair for Workshops and Tutorials: Takahiro Hanyu

Vice-Chair for Technical Activities:
Marek Perkowski (1998-1999)
Dept. of Electrical Engineering
Portland State University
Portland, OR 97207-0751
USA
Phone: (503) 725-5411
Fax:
Email: mperkows{at}ee.pdx.edu

Vice-Chair for Publicity and Marketing:
Ivan Stojmenovic
Department of Computer Science
University of Ottawa
Ottawa, Ont, K1N 6N5
Canada
Phone: (613) 739-7402
Fax: (613) 739-4396
Email: ivan{at}csi.uottawa.ca

Secretary
D. Michael Miller (1998-1999)
Dept. of Computer Science
University of Victoria
P.O.Box 3055
Victorial, B.C.
Canada V8W 3P6
Phone: 604-721-7220
Fax: 604-721-7292
Email: mmiller{at}csr.csc.uvic.ca

Treasurer
Okihiko Ishizuka (1998-1999)
Dept. of Electronic Engineering
Miyazaki University
Gakuen-Kibana Miyazaki-Shi 8809-21
Japan
Phone: +81-985-58-2811
Fax: +81-985-58-2876
Email: ishizuka{at}esl.miyazaki-u.ac.jp

Past Chair
Michitaka Kameyama (1998-1999)
Department of Computer and Mathematical Sciences
Graduate School of Information Sciences
Tohoku University
Aoba, Aramaki,Aoba-ku
Sendai 980-77
Japan
Phone: +81-22-217-7152
Fax: +81-22-163-9405
Email: michi{at}kameyama.ecei.tohoku.ac.jp

Bulletin/Web Page Editor
Yutaka Hata
Department of Computer Engineering
Himeji Institute of Technology
2167, Shosha, Himeji 671-22
Japan
Phone:+81-792-66-1661
Fax:+81-792-66-8868
Email:hata{at}comp.eng.himeji-tech.ac.jp

Executive Sub-Committee

Gerhard Dueck

Takahiro Hanyu

Marek Perkowski

Ivan Stojmenovic

D. Michael Miller

Okihiko Ishizuka

Michitaka Kameyama

Members at Large

Takafumi Aoki(1995-1998)
Graduate School of Information Sciences
Tohoku University
Sendai 980-77
Japan
Phone:+81-22-217-7169
Fax:+81-22-263-9406
Email:aoki{at}higuchi.ecei.tohoku.ac.jp

Rolf Drechsler(1995-1998)
Institute of Computer Science
Albert-Ludwigs-University
Am Flughafen 17
79110 Freiburg im Breisgau
Germany
Phone:+49-761-203-8145
Fax:+49-761-203-8142
Email:drechsle{at}informatik.uni-freiburg.de

Vlad P. Shmerko (1997-2000)
Institute of Computer Science & Information Systems
Technical University of Szczecin
Al.Piastow 41, 71-065, Szczecin
Poland
Phone:+48-91-346-214
Fax:+48-91-340-946
Email:shmerko{at}beta.ii.tuniv.szczecin.pl

Glenn Gulak(1997-2000)
Department of Electrical and Computer Engineering
10 King's College Road
University of Toronto
Toronto, Ontario
Canada M5S 1A4
Phone:416-978-8671
Fax:416-971-2286
Email:gulak{at}eecg.toronto.edu

Mou Hu (1998-2001)

Takao Waho
NTT Systems Electronics Laboratory
Kanagawa 243-01
Japan
Phone: +81-462-40-2907
Fax: +81-462-40-2872
Email: waho{at}aecl.ntt.co.jp

Symposium Sub-Committee
Tsutomu Sasao(ISMVL-98 Symposium Chair)
Department of Computer Science and Electronics
Kyusyu Institute of Technology
Iizuka
Fukuoka 820
Japan
Phone:+81-948-297675
Fax:+81-948-292603
Email:sasao{at}cse.kyutech.ac.jp

Jon Butler(ISMVL-98 Symposium Co-Chair)
Department of Electrical & Computer Engineering
Naval Postgraduate School, Code EC/BU
Monterey, CA 93943-5121
USA
Phone:408-656-3299
Fax:
Email:butler{at}cs.nps.navy.mil

Michitaka Kameyama(ISMVL-98 Program Chair)

Dan Simovici(ISMVL-98 Program Co-Chair)

Reiner Haehnle(ISMVL-98 Program Co-Chair)
Department of Computer Science
University of Karlsruhe
Karlsruhe
Germany 76128
Phone:+49-721-608-4329
Fax:+49-721-608-4329
Email:reiner{at}ira.uka.de

Gerhard Dueck(ISMVL-97 Symposium Chair)
St.Francis Xavier University
Dept. of Math. & Comp Sci.
Antigonishi,NS
B2G 2W5
Canada
Phone:902-863-6506
Fax:902-867-2448
Email:gdueck{at}stfx.ca

D.Michael Miller(ISMVL-97 Program Chair)

Rolf Drechsler(ISMVL-97 Program Co-Chair)

Okihiko Ishizuka(ISMVL-97 Program Co-Chair)
Deptartment of Electronic Engineering
Miyazaki University
Gakuen-Kibana
Miyazaki 809-21
Japan
Phone:+81-985-58-2811
Fax:+81-985-58-2876
Email:ishizuka{at}esl.miyazaki-u.ac.jp

Dan Simovici(ISMVL-96 Symposium Co-Chair)

Enric Trillas(ISMVL-96 Symposium Chair)
Department de Inteligencia Artif.
University Polytechnica de Madrid
Boadila del Madrid
Madrid 28660
Spain
Phone:+34-1-627-0385
Fax:+34-1-677-3986
Email:

Claudio Moraga(ISMVL-96 Program Chair)

Charles B.Silio(ISMVL-96 Program Co-Chair)
Department of Electrical Engineering
University of Maryland
College Park
Maryland 20742-3285
USA
Phone:301-405-3668
Fax:301-314-9281
Email:silio{at}eng.umd.edu

3. WWW of ISMVL'98

Home Page for ISMVL'98 is available

We have made the web site for ISMVL'98.

http://www2b.meshnet.or.jp/~taku/sasao/ismvl98/
Contents
History of ISMVL's
Access to Fukuoka
Hotels
Invited Talks
Call for papers
Information for Foreign Visitors
Advance Program (not completed)
Registration Information (not completed)

Please visit the site and give me constructive comments.

ISMVL'98 Symposium Chair
Tsutomu Sasao

4. 7th International Workshop on
Post-Binary Ultra-Large-Scale Integration Systems

Fukuoka Software Research Park
Fukuoka, Japan
May 26, 1998
[ Tutorial ]
10:00--11:00
Chair: D. A. Simovici (University of Boston, USA)

S. Rudeanu and and G. Georgescu
(University of Bucharest, Rumania)
Gr. C. Moisil and his school in algebraic logic

(10-minute break)

[General sessions]
[Session 1]

11:10--12:30
Challenging of Multiple-Valued VLSI Circuits and Devices
Chair: T. Hanyu (Tohoku University, Japan)

11:10--11:30
T. Waho (NTT Lab., Japan)
10-GHz Multiple-Valued Circuits Using Resonant-Tunneling Devices

11:30--11:50
P. G. Gulak (Univ. of Toronto, Canada)
CMOS Field-Programmable Analog and Mixed Signal Arrays

11:50--12:10
S. Kawahito (Toyohashi Univ. of Tech., Japan)
A Mixed Sensor, Analog and Digital Architecture for a Post-Binary System LSI.

12:10--12:30
Y. Yuminaka (Gunma Univ., Japan)
Wave-Parallel Computing Paradigm Based on Multiplexing of Signals

(Lunch break)

[Session 2]

13:30--14:30
Special Issue on BDD/MDD --Part 1--
Chair: T. Sasao (Kyushu Institute of Tech., Japan)

13:30--13:50
H. Sawada, S. Yamashita and A. Nagoya
(NTT Communication Science Laboratories, Japan)
Efficient Methods for a Simple Disjoint Decomposition and a Non-Disjoint Bi-Decomposition

13:50--14:10
H. Higuchi and Y. Matsunaga
(Fujitsu Laboratories Ltd., Japan)
Improving the Efficienty of Symbolic FSM Traversal
by Dynamic Removal of Flip-Flops

(15-minute break)

[Session 3]
14:25--15:25
Special Issue on BDD/MDD --Part 2--
Chair: R. Drechsler (Albert-Ludwigs-University, Germany)

14:25--14:45
Masaki Nakanishi, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
(Oosaka University, Japan)
An Exponential Lower Bound on the Size of a Binary Moment Diagram Representing Division

14:45--15:05
B. Becker (Germany)
Word-level Decision Diagrams in Verification

15:05--15:25
E. Dubrova (Royal Institute of Technology, Sweden)
On Dependable Strategy for Dynamic Reordering Algorithms

(15-minute break)

[Session 4]
15:40--17:00
Testing in Multiple-Valued Logic Networks
Chair: V. P. Shmerko (Technical University of Szczecin, Poland)

15:40--16:00
R. Drechsler (Germany), V. Levashenko (Belarus), A. Shakirin (Belarus), S. Yanushkevich (Poland/Belarus).
Genetic Test Pattern Generation for MVL Combinational Circuits

16:00--16:20
G. Holowinski (Poland), V. Levashenko (Belarus), C. Moraga (Germany), S.Yanushkevich (Poland/Belarus).
Some New Results of Experiments on Testing MVL Combinational Circuits with the Generalized D- algorithm.

16:20--16:40
Ugur Kalay, Douglas Hall, and Marek Perkowski (Portland State University),
Minimal Universal Test Set for Single Faults in Galois-Sum-of-Products Circuits.

16:40--17:00
V. Shmerko (Poland/Belarus), S. Jaroszewicz (Poland),
D. Simovici (USA),
V.Cheushev (Belarus). Four Remarks on Minimization of Strongly
Unspecified Logic function

5. The 28th International Symposium on Multiple-Valued Logic

Advance Program
The 28th International Symposium on Multiple-Valued Logic
Software Research Park(SPR)*, Fukuoka, Japan
(* Only Banquet is held in Sea Hawk Hotel and Resort)

Tuesday, May 26

10:00-17:30 7th International Workshop on Post-Binary
ULSI Systems

17:30-18:00 Registration

18:30-20:00 Reception

Wednesday, May 27

8:00-8:30 Registration

8:30-8:45 Opening Remarks (Room A)

8:45-9:30 Session I(Room A): Invited Address
Chair: M. Kameyama (Tohoku Univ., Japan)

T. Okuda (NEC, Japan)
Advanced Circuit Technology to Realize Post Giga-bit DRAM

9:30-9:50 Coffee Break

9:50-11:05 Session IIa (Room A): Devices
Chair: K. C. Smith (Hong Kong Univ. of Science and Tech., China)

T. Baba and T. Uemura (NEC, Japan)
Development of InGaAs-Based Multiple-Junction Surface
Tunnel Transistors for Multiple-Valued Logic Circuits

T. Itoh, T. Waho, K. Maezawa and M. Yamamoto (NTT System
Electronics Lab., Japan)
Ultrafast Ternary Quantizer Using Resonant Tunneling
Devices

M. Morisue, J. Endo, T. Morooka and N. Shimizu (Hiroshima
City Univ., Japan)
A Josephson Ternary Memory Circuit

9:50-11:05 Session IIb( Room B): Cellular Array and Fault Tolerance
Chair: C. Moraga (Univ. of Dortmund, Germany)

I. Takanami (Iwate Univ., Japan)
A Note on Realizing Multiple-Valued Logic Functions
using Akers' Cells - Cell Sizes and Path Lengths -

N. Song and M. Perkowski (Portland State Univ., USA)
Minimization of Exclusive Sums of Multi-Valued Complex
Terms for Logic Cell Arrays

Y. Nagata(Univ. of the Ryukyus,Japan), D. M. Miller
(Univ. of Victoria, Canada) and M. Mukaidono(Meiji Univ.,Japan)
Minimal Test Set Generation for Fault Diagnosis in R-Valued
PLAs

11:05-11:15 Break

11:15-12:30 Session IIIa(Room A): Decision Diagrams
Chair: Y. Matsunaga(Fujitsu Lab., Japan)

H. M. Hasan Babu and T. Sasao (Kyushu Inst. of Tech.,Japan)
Design of Multiple-Output Networks Using Time Domain
Multiplexing and Shared Multi-Terminal Multiple-Valued
Decision Diagrams

M. Miller (Univ. of Victoria, Canada)and R. Drechsler
(Albert-Ludwigs-Univ., Germany)
Implementing a Multiple-Valued Decision Diagram Package

L. Macchiarulo and P. Civera (Politecnico di Torino, Italy)
Ternary Decision Diagrams with Inverted Edges and Cofactoring
- an Application to Discrete Neural Networks Synthesis

11:15-12:30 Session IIIb(Room B):Algebra 1
Chair: T. Hikita (Meiji Univ., Japan)

H. M. Chung, S. Y. Pi (Catholic Univ. of DaeguHyosung, Korea)
and S. Rey (Catholic Univ. of Lille, France)
The MacLaurin's and Taylor's Series Expansions
of the Symbolic Multiple Valued Logic Functions

N. Takagi, A. Hon-nami and K. Nakashima
(Toyama Pref. Univ., Japan)
A Characterization of r-Valued Functions Monotonic in an
Order Based on the Regularity

L. Renren (Xiangtan Univ., China)
Some Results on the Decision for Sheffer Functions
in Partial K-Valued Logic(II)

12:30-14:00 Lunch

12:30-14:00 TC Executive Subcommittee Meeting

14:00-15:15 Session IVa (Room A): Logic Design 1
Chair: M. Perkowski (Portland State Univ., USA)

J. T. Butler (Naval Postgraduate School,USA)) and
T. Sasao (Kyushu Inst. of Tech., Japan)
On the Properties of Multiple-Valued Functions that
are Symmetric in Both Variable Values and Labels

C. Moraga and W. Wang(Univ. of Dortmund, Germany)
Evolutionary Methods in the Design of Quaternary Digital Circuits

P. Lindgren (Lulea Univ. Sweden), R. Drechsler and B. Becker
(Albert-Ludwigs-Univ., Germany)
Look-up Table FPGA Synthesis from Minimized Multi-Valued Pseudo
Kronecker Expressions

14:00-15:15 Session IVb(Room B): Logic
Chair: A. Nakamura (Meiji Univ., Japan)

R. J. Bignall and M. Spinks (Monash Univ., Australia)
Multiple-Valued Logics for Theorem-Proving
in First Order Logic with Equality

M. Baaz and R. Zach (Technical Univ. Vienna, Austria)
Compact Propositional Goedel Logics

S. Akama (Teikyo Heisei Univ., Japan) and J. M. Abe
(Univ. of Sao Paulo, Brazil)
Many-Valued and Annotated Modal Logics

15:15-15:25 Coffee Break

15:25-16:10 Session V(Room A): Invited Address
Chair: H. Yasuura (Kyushu Univ., Japan)

Z. G. Vranesic (Univ. of Toronto, Canada)
The FPGA Challenge

16:10-16:30 Break

16:30-18:10 Session VIa(Room A): VLSI Circuits 1
Chair: S. Kawahito (Toyohashi Inst. of Tech., Japan)

J. Shen, K. Tanno, O. Ishizuka and Z. Tang
(Miyazaki Univ., Japan)
Application of Neuron-MOS to Current-Mode
Multi-Valued Logic Circuits

T. Hanyu, T. Saito, and M. Kameyama (Tohoku Univ., Japan)
Asynchronous Multiple-Valued VLSI System Based on Dual-Rail
Current-Mode Differential Logic

T. Aoki and T. Higuchi (Tohoku Univ., Japan)
Set-Valued Logic Circuits for Next Generation
VLSI Architectures

Y. Yuminaka, Y. Sasaki(Gunma Univ., Japan), T. Aoki and T. Higuchi
(Tohoku Univ., Japan)
Wave-Parallel Computing Systems Using Multiple-Valued
Pseudo-Orthogonal Sequences

16:30-18:10 Session VIb(Room B): Applications of Multiple-Valued Logic
Chair: T. Kitahashi (Osaka Univ., Japan)

Y. Hata, M. Ishikawa (Ishikawa Hospital, Japan) and
N. Kamiura (Himeji Inst. of Tech., Japan)
Image Segmentation Based on Kleene Algebra

A. Ngom (Univ. of Ottawa, Canada), C. Reischer (Univ. of Quebec, Canada),
D. Simovici (Univ. of Mass., USA) and I. Stojmenovic
(Univ. of Ottawa, Canada)
Learning with Permutably Homogeneous Multiple-Valued
Multiple-Threshold Perceptrons

C. Files and M. Perkowski (Portland State Univ., USA)
An Error Reducing Approach to Machine Learning Using
Multi-Valued Functional Decomposition

C. Files and M. Perkowski (Portland Sate Univ., USA)
Multi-Valued Functional Decomposition as a Machine Learning Method

Thursday, May 28

8:00-8:30 Registration

8:30-9:45 Session VIIa(Room A): Logic Design 2
Chair: D. M. Miller (Univ. of Victoria, Canada)

B. J. Falkowski (Nanyang Technological Univ., Singapore)
Fast Multi-Polarity Complex Hadamard Transform
for Logic Functions

R. Stankovic, D. Jankovic (Univ. of Nis, Yugoslavia) and
C. Moraga (Univ. of Dortmund, Germany)
Reed-Muller-Fourier Versus Galois Field
Representations of Four-Valued Logic

L. J. Thaden (USA)
Constructing an MVL Patterned After Boolean Logic

8:30-9:45 Session VIIb(Room B): Genetic Algorithms in MVL
Chair: T. Nagata (ISIT, Japan)

Y. Yamamoto (Takasaki City Univ. of Economics, Japan)
A Synthesis Method of the Approximate Reasoning Engine
by means of Genetic Algorithm

A. Ngom, Z. Obradovic, I. Stojmenovic (Univ. of Ottawa, Canada)
Minimization of Multivalued Perceptrons using Genetic Algorithms

M. Keim, N. Goeckel, R. Drechsler, B. Becker
(Albert-Ludwigs-Univ., Germany)
Test Generation for (Sequential) Multi-Valued Logic Networks
based on Genetic Algorithm

9:45-9:55 Break

9:55-10:40 Session VIII(Room A): Invited Address
Chair: M. Morisue (Hiroshima City Univ., Japan)

P. G. Gulak (Univ. of Toronto, Canada)
A Review of Multiple-Valued Memory Technology

10:40-11:00 Coffee Break

11:00-12:15 Session IXa(Room A): Minimization
Chair: K. Yamato (Fukuoka Inst. of Tech., Japan)

T. Hozumi, O. Kakusho (Hyogo Univ., Japan)
and Y. Hata (Himeji Inst. of Tech., Japan)
On Low Cost Realization of Multiple-Valued Logic Functions

B. Fraser and G. W. Dueck (St. Francis Xavier Univ., Canada)
Multiple-Valued Logic Minimization using Universal Literals
and Cost Tables

M. H. Abd-El-Barr and M. Abd-El-Barr(King Fahd Univ.
of Petroleum and Minerals, Saudi Arabia)
A Frontier Algorithm for Optimization
of Multiple-Valued Logic Functions

11:00-12:15 Session IXb(Room B): Algebra 2
Chair: I. Stojmenovic (Univ. of Ottawa, Canada)

G. R. Pogosyan and T. Nakamura (International Christian
Univ., Japan)
e-Bases of Triadic Logic Operations

V. Cheushev (State Univ., Minsk, Belarus),
V. Shmerko (Technical Univ., Szczecin, Poland),
D. A. Simovici (Univ. of Massachusetts at Boston, USA) and
S. Yanushkevich (Technical Univ., Szczecin, Poland)
Functional Entropy and Decision Trees

G. Epstien (USA)
B-algebra and Associated Logics

12:15-13:45 Lunch

12:15-13:45 Symposium Subcommittee Meeting

13:45-15:25: Session Xa(Room A): VLSI Circuits 2
Chair: F. Ueno (Kumamoto National College of Tech., Japan)

A. Sheikholeslami, R. Yoshimura* and P. G. Gulak
(Univ. of Toronto, Canada), *(Osaka Univ. Japan)
Look-up Tables(LUTs) for Multiple-Valued, Combinational Logic

T. Hanyu, K. Teranishi, and M. Kameyama
(Tohoku Univ., Japan)
Multiple-Valued Floating-Gate-MOS Pass Logic and Its
Application to Logic-in-Memory VLSI

S. Wei and K. Shimizu (Gunma Univ., Japan)
Residue Arithmetic Circuits Based on the Signed-Digit
Multiple-Valued Arithmetic Circuits

K. Shimabukuro and C. Zukeran (Univ. of the Ryukyus, Japan)
Reconfigurable Current-Mode Multiple-Valued
Residue Arithmetic Circuits

13:45-15:25: Session Xb(Room B): Theory of Fuzzy Logic
Chair: N. Nakajima (Toyama Univ., Japan)

T. Araki, H. Tatsumi, M. Mukaidono* and F. Yamamoto
(Kanagawa Inst. of Tech., Japan), *(Meiji Univ.,Japan)
Minimization of Incompletely Specified Regular Ternary
Logic functions and its Application to Fuzzy Switching
Functions

H. Tatsumi, T. Akaki, M. Mukaidono* and S. Tokumasu
(Kanagawa Inst. of Tech., Japan), *(Meiji Univ.,Japan)
Upper and Lower Bounds on the Number of Fuzzy/C
Switching Functions

H. Thiele(Univ. of Dortmund, Germany)
On Closure Operators in Fuzzy Deductive Systems and Fuzzy Algebras

Y. Yamauchi(International Christian Univ., Japan)
and M. Mukaidono (Meiji Univ., Japan)
A Study on Operations in Interval and Paired Probabilities

15:25-15:45 Coffee Break

15:45-16:30 Session XI(Room A): Invited Address
Chair: D. Simovici (Univ. of Massachusetts at Boston, USA)

T. Shibata (Univ. of Tokyo, Japan)
Functional-Device-Based VLSI for Intelligent Electronic Systems

16:30-17:30 Plenary Session( Room A)

18:30-20:30 Banquet (Sea Hawk Hotel and Resort)

Friday, May 29

8:00-8:30 Registration

8:30-9:15 Session XII(Room A): Invited Address
Chair: A. Nozaki (Otsuma Women's Univ., Japan)

I. G. Rosenberg (Univ. of Montreal, Canada)
Multiple-Valued Hyperstructures

9:25-10:10 Session XIII(Room A): Invited Address
Chair: R. Hahnle (Univ. of Karlsruhe, Germany)

T. Yamakawa (Kyushu Inst. of Tech., Japan)
A Novel Nonlinear Synapse Neuron Model Guaranteeing
a Global Minimum --Wavelet Neuron --

10:10-10:30 Coffee Break

10:30-12:00 Session XIVa(Room A): Applications of Fuzzy Logic
Chair: Y. Koga(National Defense Academy, Japan)

C. Kahraman (Istanbul Tech. Univ., Turkey)
and E. Tolga (Galatasaray Univ., Turkey)
Data Envelopment Analysis using Fuzzy Concept

F. Wakui and M. Hirano (Nihon Univ., Japan)
A Proposal and an Application of a Career Mode
Membership Function

M. Tokumaru, K. Yamashita, N. Muranaka and S. Imanishi
(Kansai Univ., Japan)
Membership Functions in Automatic Harmonization System

N. Kamiura, Y. Hata(Himeji Inst. of Tech., Japan) and
K.Yamato(Fukuoka Inst. of Tech., Japan)
On Concurrent Tests of Fuzzy Controllers

10:30-12:00 Session XIVb(Room B): Clone Theory
Chair: M. Miyakawa(Tsukuba College of Tech., Japan)

L. Haddad and F. Borner (Royal Military College, Canada)
Generating Sets for Clones and Partial Clones

J. Fugere and L. Haddad (Royal Military College, Canada)
On Partial Clones Containing All Partial Idempotent Operations

H. Machida (Hitotsubashi Univ., Japan)
Some Continuous Maps on the Space of Clones in Multiple-Valued Logic

A. Nozaki (Otsuma Women's Univ., Japan)
and V. Lashkia (Okayama Univ. of Science, Japan)
A Finite Basis of the Set of All Monotone Partial
Functions Defined over a Finite Poset