IEEE MVL-TC Bulletin

VOLUME 18 Number 1 March 1997

1. Chair's Message

The 27th International Symposium on Multiple-Valued Logic will be held in Nova Scotia, Canada on May 28-30. This is a very important chance to discuss topics on multiple-valued logic in our international community. Also, the International Workshop on Post-Binary Ultra-Large Scale Integration is planned for May 27 in conjunction with ISMVL-97. This year, tutorial sessions are included in the Workshop program. As in the past there is no charge for the workshop and there is no charge for the tutorials. I think the tutorials will prove useful both for established researchers as well as younger researchers and MVL beginners. I invite everybody to attend ISMVL-97 and the Workshop.

Developments in multiple-valued research become more and more exciting. For an example, a 4 Gbit multiple-valued DRAM has been developed by NEC. Further, 4-valued flash memory has been made commercially available by SANYO. From the academic point of views, several technical papers closely related to multiple-valued integrated circuits were presented in the 1997 International Solid-State Circuits Conference. These include a quantum device, a multiple-valued CAM and analog signal processing .

It is a very important time to develop new innovative architectures from our community, because binary-based integrated circuits are confronted with many difficulties in the deep-submicron age. I hope all our members can have a chance to contribute to such development and evolution.

Best Regards,
Chair Michitaka Kameyama

2. MVL-TC Chair Call For Nominations

We welcome any nominations for the position of TC Chair for two year period beginning January 1,1998. The nomination should be sent to both of:

M.Kameyama (michi{at}kameyama.ecei.tohoku.ac.jp)
and
D.M.Miller(mmiller{at}csr.csc.uvic.ca)

by May 20, 1997. The final nomination will be determined in the Executive Subcommittee and the Plenary Session of the ISMVL-97.

After the nomination, an election should be required, and it will beconducted via the next issue of the Bulletin.

3. Multiple-Valued Logic -An International Journal-

I would like to refer you to our web site: http://www.gbhap.com which should be able to answer some general questions.

4 issues per volume
320 printed pages per volume (80 per issue)
Prices: Individual: $95; ECU 79; SFr 158
Academic price, $ 228; ECU:190 or SFr534
Corp: $356; ECU 296; SFr 592

Publisher: The Gordon and Breach Publishing Group

The first volume has already published. Volume 2 is the current subscription block for 1997. Back issues (Vol. 1) are available.

To order the journal, please call +44 (0) 1734 568316 or fax 44 (0) 1734 568211 or in North/South America: 1-800-545-8398 or fax (215) 750-6343

Please let me know if you require further information.

Thanks.

Catherine
catherine.bewick{at}gbhap.com

4. ISMVL-97 : An Invitation

It is my pleasure to extend an invitation to everyone who has an interest in MVL to attend the 1997 International Symposium on Multiple-Valued Logic. This is the fourth time that the Symposium is held in Canada and it is the first time that the event takes place in Nova Scotia. The annual ISMVL is the principal forum for the exchange of research developments in all aspects of multiple-valued logic.

The program committee has put together an excellent program. As in the past, papers cover a wide range of topics. Details about the program are included in this bulletin and are also available at http://juliet.stfx.ca/~gdueck/ismvl97/. I like to draw your attention to the invited speakers -- the titles of their talks suggest new challenges.

Antigonish is located in northeastern Nova Scotia with a population of 6,000. The surrounding countryside is beautiful and has its own unique charm. Trout rivers, the best of salmon fishing, a ski hill and a variety of beaches and waterfront vistas, are only a few of the many attractions to be found a short distance from town. For the banquet we will take a trip to Liscombe Lodge. There we can unwind as the chefs cook up the house specialty, planked salmon -- it's prepared in the traditional way, slowly cooked outdoors in full view of waiting diners.

I invite you to explore Nova Scotia after or before the Symposium. Check the website http://www.destination-ns.com/main.htm to help you with your travel plans. Spring arrives late in Nova Scotia. The nights can still be quite cold at the end of May. Please come prepared to face a cold breeze from the ocean.

I look forward to hosting ISMVL-97. Please do not hesitate to contact me if I can assist in your plans for your visit to Antigonish.

Gerhard Dueck
Symposium Chair ISMVL-97

ISMVL-97 : ADVANCE PROGRAM

May 27

1800-2000 Reception and Registration
Faculty Lounge (6th floor of Nicholson Hall) at St. F. X.

May 28

0800-0900 Registration
(All technical sessions will be at the Best Western Claymore Inn.)

0900-0915 Opening Remarks (Chisholm Room)

0915-1015 Session 1: Invited Address (Chisholm Room)
Recent Developments in DNA-Computing,
D. Rooß , Institut für Informatik, University of Würzburg, Germany

1015-1045 Break

1045-1215 Session 2a: Decomposition (Chisholm Room)
Decomposition of Multiple-Valued Relations,
M. Perkowski, M. Marek-Sadowska, L. Jozwiak, T. Luba, S.
Grygiel, M. Nowicka, R. Malvi, Z. Wang and S. Zhang
Finding Composition Trees for Multiple-Valued Functions,
E. Dubrova , J. C. Muzio and B. von Stengel
Functional Decomposition of MVL Functions, C. Files ,
R. Drechsler and M. A. Perkowski

1045-1215 Session 2b: Technology (Cameron Room)
Application of Resonant-Tunneling Quaternary Quantizer to Ultrahigh-Speed
A/D Converter,
T. Waho, and M. Yamamoto
Multiple-Junction Surface Tunnel Transistors for Multiple-valued Logic Circuits,
T. Baba and T. Uemura
Enzyme Transistor Circuits for Bioolecular Computing,
M. Hiratsuka, T. Aoki and T. Higuchi

1215-1330 Lunch & Executive Subcommittee Meeting

1330-1500 Session 3a: Minimization I (Chisholm Room)

Comparison of the Worst and Best Sum-of-Products Expressions for
Multiple-Valued Functions,
J. T. Butler and T. Sasao
Fast Algorithm for Minimizing Reed-Muller Expansions of Systems of
Incompletely Specified MVL Functions,
A.D. Zakrevskij and L.A. Zakrevski
Fast Exact Minimization of Fixed-Polarity Multi-Valued Linear Functions,
R. Drechsler , M. Keim and B. Becker

1330-1500 Session 3b: Algebra (Cameron Room)
Completeness Criteria in Set Logic Under Compositions with Union and
Intersection,
I. Stojmenovic , A. Ngom, C. Reischer and D. A. Simovici
Hyperclones on a Finite Set,
B. Romov
Set-Valued Functions and Regularity,
N. Takagi, Y. Nakamura and K. Nakashima

1500-1530 Break

1530-1630 Session 4a: Minimization II (Chisholm Room)
Multiple-Valued Logic Minimization by Genetic Algorithms,
Y. Hata, K. Hayase and T. Hozumi
Multiple-Valued Product-of-Sums Expression with Truncated Sum,
Y. Hata, N. Kamiura and K. Yamato

1530-1630 Session 4b: Philosophical Aspects (Cameron Room)
Representation of uncertain belief using interval probability,
P. H. Giang
What is Many-Valued Logic?
J.-Y. Béziau

1630-1730 Session 5a: Spectral Techniques (Chisholm Room)
Family of Complex Hadamard Transforms: Relationship with Other Transforms
and Complex Composite Spectra,
S. Rahardja and B. J. Falkowski
Properties and Applications of Unified Complex Hadamard Transforms,
B. J. Falkowski and S. Rahardja

1630-1730 Session 5b: Testing and Fault Simulation (Cameron Room)
Test Pattern Generation for Combinational Multi-Valued Networks Based
on Generalized D-Algorithm,
V. Shmerko, S. Yanushkevich and V. Levashenko
Fault Simulation in Sequential Multi-Valued Logic Networks,
R. Drechsler , M. Keim and B. Becker

May 29

0900-1000 Session 5: Invited Address (Chisholm Room)
Manyvaluedness and Uncertainty
E. Orlowska, Institute of Telecommunications, Warsaw, Poland

1000-1030 Break

1030-1200 Session 6a: Circuit Applications (Chisholm Room)
Multiple-Valued Programmable Logic Arrays with Universal Literals,
T. Utsumi, N. Kamiura, Y. Hata and K. Yamato
LSI design of a quaternary multiplier with direct generation of partial
products,
O. Ishizuka, A. Ohta, Dwi Handoko, K. Tanno and Z. Tang
One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic
Image Processing,
T. Hanyu, M. Aragaki and M. Kameyama

1030-1200 Session 6b: Fuzzy Logic (Cameron Room)
On the Mutual Definability of Classes of Generalized Fuzzy Implications
and of Classes of Generalized Negations and S-Norms,
H. Thiele
On Training Fuzzy Logic Based Software Components,
J. Chen and D. C. Rine
Properties of Fuzzy and a-driven Lindenmayer Languages,
E. Meyer zu Bexten and C. Moraga

1200-1330 Lunch & Symposium Subcommittee Meeting

1330-1500 Session 7a: Circuits (Chisholm Room)
A Useful Application of CMOS Ternary Logic to the Realisation of
Asynchronous Circuits,
R. Mariani, R. Roncella, R. Saletti and P. Terreni
Design of Ternary CCD Circuits Referencing to Current-Mode CMOS Circuits,
X. Wu and M. Pedram
Quaternary Dynamic Differential Logic with Application to Fuzzy-Logic Circuits,
A. Herrfeld and S. Hentschke

1330-1500 Session 7b: Applications (Cameron Room)
A Proof Method for the Six-Valued Logic for Incomplete Information,
Seiki Akama
Multiple-Valued Logic as a Programming Language,
R.J. Bignall and M. Spinks
Multiple-Valued Immune Network Model and Its Simulations,
Z. Tang, T. Yamaguchi, K. Tashima, O. Ishizuka and K. Tanno

1500-1515 Break

1515-1600 Plenary Session (Chisholm Room)

Evening Banquet

May 30

0900-1000 Session 8: Invited Address (Chisholm Room)
Ternary Decision Diagrams: Survey
T. Sasao, Department of Computer Science and Electronics,
Kyushu Institute of Technology, Japan

1000-1030 Break

1030-1200 Session 9a: Logic Design (Chisholm Room)
On The Synthesis of MVL Functions Using Input and Output Assignments,
M. Abd-El-Barr, G. A. Hamid and M. N. Hasan
Mixed Discrete Optimization of Multiple-Valued Systems,
A. Etzel
Design of an Asynchronous Digital Sytem with B-ternary Logic,
Y. Nagata and M. Mukaidono

1030-1200 Session 9b: Function Representation (Cameron Room)
Circuit Design from Galois Field Decision Diagrams for Multiple-Valued Functions,
R. Stankovic and R. Drechsler
Fourier Decision Diagrams on Finite Non-Abelian Groups with Preprocessing,
R. Stankovic
Cube Diagram Bundles: A New Representation of Strongly Unspecified
Multiple-Valued Functions and Relations,
S. Grygiel, M. Perkowski, M. Marek-Sadowska, T. Luba and L. Jozwiak

1200-1215 Closing Remarks (Chisholm Room)

6th Workshop on Post-Binary
Ultra-Large-Scale Integration Systems

St. Francis Xavier University
Antigonish, Nova Scotia, Canada

May 27, 1997

Invitation

It has become traditional to hold the Post-Binary Workshop in conjunction with the International Symposium on Multiple-Valued Logic. This year is no exception. The aim of workshop is not only to discuss hot topics of interest to MVL researchers, but also to encourage MVL researchers to explore new avenues. Professor Takahiro Hanyu has assembled a very promising list of speakers. You are cordially invited to participate. As in the past, registration for this event is free.

Program

[ Tutorial ]
9:00--12:35
Tutorial 1
9:00--9:50
Completeness, Composition and Clones in Multiple-Valued Logics
Prof. Ivo G. Rosenberg (University of Montreal, Canada)
Tutorial 2
9:55--10:45
Fuzzy Logic and Its Mathematical Properties
Prof. Masao Mukaidono (Meiji University, Japan)
Tutorial 3
10:50--11:40
Multiple-Valued Logic Design
Prof. Jon T. Butler (Naval Postgraduate School, USA)
Tutorial 4
11:45--12:35
Multiple-Valued VLSI Circuits and Systems
Prof. Charles B. Silio, Jr. (University of Maryland, USA)

[General sessions]
14:00--17:30
Session 1
14:00--15:00
Minimization of Incompletely Specified Logic Functions
Chair: Prof. Vlad P. Shmerko (Technical University of Szczecin, Poland)

(1) Hardware Realization to Minimize Incompletely Specified Functions
Prof. M.Perkowski (USA)
(2) Minimization of Partially Mixed Polarity Reed-Muller Expansions
Dr. B.J.Falkowski and C.H.Chang (Singapoore)
(3) Title --now considering--
Prof. Z.Zilic or Dr.Z.Vranesic (Canada)
(4) Efficient Algorithm for Minimization of Polynomial Representations of Weakly Specified Boolean functions and Systems
Dr. L. Zakrevsky (Belarus)
(5) Parallel and Distributed Realization of Irredundant Minimization of MVL Functions
Prof. V. P. Shmerko, G.Holowinski, Dr.S.Yanushkevich
(Poland)

Session 2
15:05--16:05
Fuzzy Logic and Its Applications
Chair: Prof. Yutaka Hata (Himeji Institute of Technology, Japan)

(1) On the Computational Power of Continuous Dynamical Systems
Mr. Olivier Bournez (France)
(2) Fuzzy Optimization of Industrial Power Plants
Dr. Andreas Etzel (Germany)
(3) Fuzzy Medical Image Processing
Prof. Yutaka Hata (Japan)

Session 3
16:10--17:30
Challenging of Multiple-Valued VLSI Circuits and Devices
Chair: Prof. K. C. Smith (The Hong Kong University of
Science & Technology, Hong Kong)

(1) New Architecture for Multiple-Valued VLSI Systems
Prof. Michitaka Kameyama (Tohoku University, Japan)
(2) Beyond-Binary Arithmetic
Prof. Takafumi Aoki (Tohoku University, Japan)
(3) Multivalued Ferroelectric Associative Memory Design
Prof. P. Glenn Gulak (University of Toronto, Canada)
(4) MVL Circuits with Quantum Devices
Dr. Takao Waho (NTT System Electronics Lab., Japan)

ISMVL-97 Registration

Name: (Last)_______________________(First) ____________________________

IEEE Member Number: ________________

Affiliation: __________________________________________________________

Address: __________________________________________________________

__________________________________________________________

City: _______________________ Province/State: ___________________________

Country: ____________________ Postal/Zip Code: ________________

Telephone: ___________________________ Fax: __________________________

email: ______________________________________

I will _____ will not ____ attend the Post Binary ULSI Workshop on May 27
(there is no charge)

Fee Schedule (in Canadian Dollars) please circle the appropriate fee

Before Apr. 30, After Apr. 30,

IEEE Members $350 $420
Non Members $440 $525
Students $50 $70

Regular registration includes all social events and a copy of the proceedings.
Student registration include a reception and a copy of the proceedings-
not the luncheons or banquet.

_____ additional banquet tickets ($50) _____ additional proceedings ($40)

Method of payment:

1.By cheque or money order payable to St. Francis Xavier University
in Canadian dollars.
2.Charge the amount of __________ to ____ VISA, _____Mastercard ______ AMEX

Card # _____________________________________________

Exp. Date __________________________________________

Name on the Card ____________________________________

Signature ___________________________________________

Please send mail to:

Gerhard Dueck
Dept. of Math. and Comp. Sci.
St. Francis Xavier University
Antigonish, Nova Scotia,
B2G 2W5 Canada

MVL-97 Accommodation Form

Name: (Last)_______________________(First) ____________________________

Address: __________________________________________________________

City: _______________________ Province/State: ___________________________

Country: ____________________ Postal/Zip Code: ________________

Telephone: ___________________________ Fax: __________________________

email: ______________________________________

Arrival Date_________________ Departure Date ______________________

Type of Room (please circle your choice):

1 double bed $63.00 Canadian Smoking only

1 queen bed $65.00 Canadian Smoking or non Smoking

1 king bed $99.00 Canadian Smoking or Environmentally clean

2 double beds $69.00 Canadian Smoking or non Smoking

Prices are for two adults per room plus 15% tax. Additional adults $5.00
Canadian. For environmentally clean rooms additional $10.00 Canadian.
Rooms will be assigned on a first request basis.

A block of rooms will be held until May 2, 1997. After this date reservation
will be accepted on a space available basis. Provide credit card information
or send a cheque or money order payable to the hotel to cober one night's
accommodation in Canadian funds. Deposit is fully refundable, if the
reservationn is cancelled before 16:00 on the day of the arrival.

Credit Card information: __VISA, __ Mastercard, ___AMEX, ___ Diners ____ EnRoute

Card # _____________________________________________

Exp. Date __________________________________________

Name on the Card ____________________________________

Signature ___________________________________________

Please send mail to:

Best Western Claymore Inn
Church St., Box 1720
Antigonish, Nova Scotia
B2G 2M5, Canada

Fax: (902) 863-1050

Toll free registration: 1-888-863-1050

Getting to Antigonish

You can reach Nova Scotia by air, land or sea.
.
Antigonish is approximately 200 Km from the Halifax International Airport. Take highway 102 north to Truro. Trun east on Highway 104 (towards Cape Breaton). In Antigonish, take Exit 33 (Church St.) The Best Western Claymore Inn is visible from the Exit (behind Sobey's Foo dStore.)

Rent a Car

There are several car rental agencies at the Halifax airport. For reservations with Thrifty call 1-800-3672277. Current covention rates for Thrifty are $42 per day and $252 per week, unlimited KMs. (Prices are in Canadian Dollars.) You may also want to check Dollar or Avis.

Take the Bus

Acadian Lines has the following daily departures from Halifax Airport:
Airport Departure 8:45 13:15 16:25 19:10
Antigonish Arrival 11:30 16:25 19:10 22:20

The bus fare is $21.50 each way. The airport is quite a way from Halifax.

Share a Ride

If you plan to rent a car, please let Gerhard Dueck know when you plan to arrive and how many people could get ride with you. He will post your message on the ISMVL web site so people can contact you.

Stay in Halifax for a Day

Should you arrive too late to catch the last bus to Antigonish, you can stay in the hotel at the airport. Halifax International Airport is about 40 km (25 miles) from downtown Halifax and about 35 km (21 miles) from downtown Dartmouth. Airbus drops passengers off daily at all major Halifax and Dartmouth hotels ($11 one-way,
$18 return), beginning at 6:30a.m. The last bus leaves the airport at 10:45p.m. Call (902) 873-2091 for further information.

5. IEEE Data base for TC members

We are editing MVL Group Data base, Please send your personal data to hata{at}comp.eng.himeji-tech.ac.jp.