It is with great pleasure for me to announce that the review of the Multiple-Valued Logic Technical Committee (MVL TC) was successful. According to an IEEE Computer Society regulation, every technical committee (TC) is reviewed every four years. The presentation for the review and the discussion was conducted in the Technical Activities Board Meeting (TAB) held in Pittsburgh on November 20, 1996. Profs. Jon T.Butler, Charles B. Silio and Michel Israel supported my presentation on activities of the MVL TC. I thank them for their cooperation on behalf of the TC.

We have confirmed that our activity is excellent, and we have to continue such vitality also in the future. I expect that the vitality of our TC depends not only on continuing established activity, but also on new activity. Especially, we must encourage younger researchers toward the future activity. I welcome your innovative ideas. We must make our research attractive, so that the younger generation naturally becomes interested in MVL.

In the TAB meeting, leadership of each TC is strongly requested from the view point of the Society development. I hope everyone has chance to contribute to our TC strong leadership through research activity.

Chair Michitaka Kameyama

The IEEE Data base for TC member lists will be renewed by the end of this year (Dec. 31, 1996). Even all of already registered members should send your data to: IEEE Computer Society.
Every time, only a few people respond to our request! Unless you send your data to us, you loose your membership advantages to get useful informations such as a new research trend!!
Please take only a few minitues to send your data such as your name, E-mail address and so on !!!
click here for application form

Moreover, we are editing MVL Group Data base, Please send your personal data to hata{at}comp.eng.himeji-tech.ac.jp.

The following Journal has been already published. Please contact International Publishers Distributer (info{at}gbhap.com, fax +1 215 750 6343) if you are interested in the journal.

Volume 1 Issue 1: Editorial
Lotfi Zadeh:
Fuzzy logic and calculi of fuzzy rules and fuzzy graphs
Tsutomu Sasao and Jon Butler:
Planar Decision Diagrams for Multiple-Valued Functions
E. V. Dubrova and J. C. Muzio:
Generalized Reed-Muller canonical Form for a Multiple-Valued Algebra

Issue 2:
Helmut Thiele:
On mathematical foundations of fuzzy cluster analysis
Kilgus B. and D. Schweigert:
Representations by order-polynomially complete lattices
Dejan Zivkovic:
A note on computing the OR and AND gate by a probabilistic depth-2 circuit
G. Epstein, B. W. Prentice, H. M. Razawi, E. N. Spring:
Optimal Codings for Binary-Coded Quaternary Adders

Issue 3:
X. Deng, T. Hanyu, and M. Kameyama
Synthesis of multiple-valued logic networks based on super pass gates
Chung Len Lee:
Complete Test Set Generation for Multiple-Valued Logic Networks
D. Dubois and H. Prade:
Combining Hypothetical Reasoning and Plausible Inference in Possibilistic Logic

Challenges and opportunities in the 21st century include the Nanoelectronic Revolution which will give us a rich new arsenal of tools for implementing multiple-valued logic (MVL), either by itself or in synergistic fashion with its special case, the pervasive binary logic.

The MVL circuit specialist and logic designer must explore and utilize the many new semiconductor and optoelectronic phenomena, strucures and devices that are presently under investigation in many laboratories world wide; a few examples of these new nanoelectric structures are
--Sawtooth functions generated by RTD stacks
--Staircase voltage functions: generated by single-electron devices
--Deliberate threshold-setting by lateral design: in Tunneling HEMTs
--Current, voltage and photon-stream tailoring and summation
--Lateral branching and vertical tunneling: in Tunneling HEMTs
--Folding circuits with RTD stacks: for large fan-in XOR, XNOR; and for Radix-2 MVL, analog-to-digital converters, and MV memory cells

Your contribution addressing such topics is solicited for a special issue of

Multiple-Valued Logic --an International Journal entitled
"Nanoelectronics -- the Next Generation of Multiple-Valued Logic."

The area of interest covers concepts, new work, and systematic tutorial treatment in all of the following areas
but is not limited to it.

(1) Nanoelectronic (semiconductor) phenomena, structures, devices and circuits that exhibit well-defined multiple-valued signals and lend themselves to implementing MV logic and computational arrays. Signal representation can be with voltages, currents, photon streams or otherwise.

(2) Nanoelectronic phenomena, structures, devices and circuits similar to the types described in (1) that are suited for signal representation and signal processing equally well in binary logic, radix-2 MVL, and higher-radix MVL (>2).

(3) New MVL synthesis methods and design procedures addressing specific items under (1) and (2), or existing ones that are modified to encompass them.

(4) Systems- or circuit-oriented theoretical work addressing and postulating new nanoelectronic device types or parameters for guiding the ongoing or future nanoelectronic technology research (the "top-down" approach).


NANOELECTRONICS is defined here as any integrated semiconductor technology (electrical and optoelectronic) that has NANOMETER critical or vital dimensions, or as one whose critical dimensions are "smaller than those of classical Microelectronics"(about 0.1 micrometers laterally). This includes resonant tunneling devices with larger lateral dimensions but with "nanometer" vertical barrier and well dimensions.
It also includes a mix of classical and nanoelectronic and/or quantum devices.


The first part of the Special Issue will have full papers,in part invited, addressing this area in a systematic and coherent way. It is contemplated that these papers would be suitable for future publication in book form.

The second part of the Special Issue will have short papers of a "brainstorming" nature in order to discuss nanoelectronic possibilities, challenges and prospects well into the next century: to stimulate and ferment future scientific work in this promising area.

Please submit a one-page summary (300-500 words) of your intended submission, indicating "for Part I" or "Part II,"

via e-mail to all of the following addressees:

Lutz Micheel micheel{at}el.wpafb.af.mil

We'll then in Feb 97 provide you with a list of the editorial board for the Special Issue, the schedule for the further submissions of Abstract and Full Paper, and an answer as to the suitability of your submission for this issue.

The aim of this workshop is not only to discuss hot topics of current MVL (or related to MVL) researches, but also to encourage `young' and `fresh' MVL researchers. From the above points of view, I have prepared four tutorials before starting general sessions in the program of the 1997 workshop.

No. 1. Set-Valued Logic Functions and Regularity
Y. Nakamura, N. Takagi and K. Nakashima
(Toyama Prefectural University)
Multiple-valued logic functions with a power set as the set of truth values are called set-valued logic functions (SVL functions). In our former works, we have clarified fundamental properties and a necessary and sufficient condition for SVL functions monotonic in the set-theoretical inclusion (monotone SVL functions). Furthermore, we have given simplified logic expression of monotone SVL functions. Kleene has introduced regularity on ternary logic connectives. Moreover, Mukaidono has expanded Kleene's regularity into the n-variable ternary functions. In this paper, we will extend the concept of Mukaidono's regularity into the SVL functions. The SVL functions which satisfy the regularity are called regular SVL functions. We will then compare the logic expressions of regular SVL functions with the monotone SVL functions. Furthermore, we will define some new type operations, and be able to show that these operations enable us to obtain two necessary and sufficient conditions for regular SVL functions.

No. 2. Implementation of Set-Valued Logic Functions by Hybrid Structure
M. Kurosaki, N. Takagi and K. Nakashima
(Toyama Prefectural University)
A possible model of molecular switching devices based on enzyme-substrate interaction is proposed to construct a new type of logic network called ``Set Logic Network''. The mathematical properties of the model are considered for the systematical synthesis of set logic functions (SVFs). Furthermore, we can construct every SVF by feeding boolean functions into bio-output generators which are considered as SVFs. In this construction, we can find some merits because we can apply the properties of the boolean functions to the construction of SVFs. But, we cannot use arbitrary boolean functions for a given SVF. In this paper, we clarify conditions those boolean functions should satisfy.

No.3 On Orthogonal Expandabilities
N. Takagi *and H. Kikuchi**
(*Toyama Prefectural University and** Tokai University)
This paper studies an issue of orthogonal expandable, that is, given function can be divided into several smaller subfunctions. Also, sub-orthogonal expansion in which an input space is partitioned into some subsets that are not disjoint is discussed. The main results is that both expansions are not functional complete, and a proposal of simple algorithm to obtain a meaningful sub-orthogonal expansion.

No.4 On Orthogonal Functions
G. Pogosyan
(I.C.U.)
A year ago, at the previous Forum of the Japan Research Group on MVL, the author presented a paper where the notion of orthogonal expansion of finite valued logic functions was introduced. We saw that the orthoexpandable functions, i.e. those that allow a non-trivial orthogonal expansion, essentially improve the average optimal complexity of circuit implementation. However, as it was proved, the ratio of orthoexpandable n variable functions to the number of all functions of n variables tends to zero with n approaching to infinity. This ratio is even smaller when so called ortholinear (i.e. perfectly expandable) functions are considered. In this note we continue talking about the "few, but precious" orthoexpandable and ortholinear functions. We see that, although their ratio to all functions is infinitely small, there is still quite a large number of them, and this number increases exponentially with the growth of n. In the particular case of three-variable Boolean functions 152 out of all 256 functions are ortholinear. Using an algorithm based on the properties of the ortholinear functions, we could easily find all 152 of them. The list of these functions, each presented by its unique mod2 polynomial and an ortholinear form, is given in Appendix.

No. 5 Functional Freeness for Some Class of Algebras
M. Kondo
(Shimane University)
In this paper we show that an algebra Q(m, n) is functionally free for the Berman class Kmn of Ockham algebras, that is, for any two polynomials f and 9, they are identically equal in Km,n if and only if f = g holds in Q(m, n). This result can be applied to the well-known algebras, e.g., Boolean, de Morgan, Kleene, Stone algebras, and so on.

No.6 On Generation of Finite Fuzzy Algebras
H. Tatsumi and T. Araki
(Kanagawa Institute of Technology)
A fuzzy algebra described in this paper is obtained from a Boolean algebra by replacing the complementary low being satisfied by a Boolean algebra with the weaker condition, called Kleene's law, in axioms of a fuzzy algebra. A set of complete and independent axioms, comprising six axioms, for the above fuzzy algebra is already clarified. Therefore, we can judge whether any given model satisfies a fuzzy algebra by simply examining each axiom of it. Based on the judging procedure which is reforming more speedily, we enumerate the finite fuzzy algebra having n elements for n=3 to n=13, and give the Hasse's diagrams of complete generating results.

No.7 Fixed-Cores of Kleene Algebras and DeMorgan Algebras
N. Nakajima* and M.Morioka**
(*Toyama University and **Miyagi University of Education)
We define a fixed- core (with respect to the negation N) of a deMorgan algebra as the smallest interval I that satisfies N(I) = I. We show that (1) any deMorgan algebra has fixed- cores; (2) fixed- cores, if they do not degenerate to fixed- points, are Boolean algebras; (3) the necessary and sufficient condition for a deMorgan algebra to be a Kleene algebra is it has just one fixed- core; and (4) any deMorgan algebra has fixed-cores of the same size.

No. 8 Completeness of Lukasiewicz Logic Functions
N. Takagi*, K. Nakashima* and M. Mukaidono**
(*Toyama Prefectural University and **Meiji University)
The literal, TSUM, INV (negation), min, and max operations employed in multiple-valued logic design can be expressed in terms of the implication and the negation of Lukasiewicz many-valued logic. We can easily show that the set of multiple-valued functions composed of the above five operations is equivalent to the set of all multiple-valued functions composed of the Lukasiewicz implication and the negation. This implies that from the viewpoint of the multiple-valued logic design, Lukasiewicz multiple-valued logic is a fundamental system. In this paper, we clarify a necessary and sufficient condition for a multiple-valued function to be a Lukasiewicz logic function, which is defined as a function in terms of the Lukasiewicz implication and the negation. Our result is constructive, in other words, we can always construct a logic formula of a multiple-valued function whenever the multiple-valued function satisfies the necessary and sufficient condition.

No.9 Multiple-Valued Logic Design Based on Genetic Algorithm
K. Hayase, T. Hozumi, N. Kamiura, Y. Hata and K. Yamato
(Himeji Institute of Technology )
This paper describes an approach to minimize multiple-valued logic expressions by genetic algorithms. We encode a multiple-valued logic expression as a "chromosome" whose length allows to change and corresponds to the number of implicants of the expression. Our fitness function evaluates the following three items: 1. How may outputs does the logic expression represent correctly? 2. How many implicants the logic expression requires? 3. How many connections does the logic expression requires? Our method employ the fitness function and minimize sum-of-products expressions, where sum refers TSUM or MAX and product refers to MIN of set literals or window literals. The simulation results show that our method derive good results for some arithmetic functions and intend to avoid the local minimal solution, compared to neural-computing-based method.

No.10 A Neuro-Fuzzy Computing Model of Human Pattern Generation
Y. Hata, N. Kamiura and K. Yamato
(Himeji Institute of Technology )
This paper investigates a novel technique for constructing and evaluating neuro-fuzzy models of similar pattern generation. The modeling approach consists of two steps: first a neural network is trained to learn a core concept and then the trained network is augmented with additional processing nodes and connections. The augmented network is then tested on its ability to solve problems related to the core concept for which it was trained. We present results from applying our model to generation of binary monotone-functions, image generation and decision making.

No.11 An Application of Jisjoint Disjunctive Form to Reliability Analysis
of Communication Networks.
T. Araki and H. Tatsumi
(Kanagawa Institute of Technology)
This paper, at first, describes a new algorithm to calculate availabilities of communication networks by using principle of optimality of dynamic programming (DP). It is well known that state space decomposition method is one of problems of NP-hard. However, it is important to reduce computational complexity. The proposed algorithm gives a procedure to save the size of binary tree on the way of state space decomposition. Secondly, we propose the method to estimate the size of binary trees generated in the above process by using logic formulas in disjoint disjunctive form. We had result that the proposed algorithm generated almost minimal binary trees.

No.12 Applications of Multiple-Valued Logic on Safety-Related Systems
M. Sakai*, K. Futsuhara* and M. Mukaidono**
(*Nippon Signal Co., Ltd. and **Meiji University)
This paper describes applications of multiple-valued logic for evaluating safety. A risk assessment for evaluating the safety of safety-related work systems is proposed. The method was proposed to ISO as the proposal of Japan Working Group. And a hazard analysis for verifying the safety performances of the sensor based on dynamic fail-safe negation is presented. The safety of the sensor was tested and certified as the highest category defined by European Standard:prEN954.

No.13 Asynchronous Systems with B-3 Logic
Y. Nagata* and M. Mukaidono**
(*University of the Ryukyus and **Meiji University)
Recently, digital systems have a serious problem that is clock skew which comes from huge hardware implementations and high speed operations in VLSI's. To overcome this problem, clock distribution techniques and, notably, asynchronous system design methodologies have been investigated forcefully. Since the asynchronous digital system is conventionally designed using two-rail logic with two-phase data transfer, more than two-fold hardware is required in comparison with synchronous system. In this article, we proposed asynchronous digital systems exploiting B-ternary logic. This system has some advantages: (1)less hardware costs (interconnections and transistors), (2)hazard-free and (~)less computation time in operating-phases. We introduce B-ternary logic, and provide a guideline of design methodology on the ternary asynchronous system which consists of a data-path and a controller.

No.14 Set-Valued Logic Networks Using Pseudonoise Sequences
T. Nakanishi, T. Aoki and T. Higuchi
(Tohoku University)
This paper presents set-valued logic networks using pseudonoise sequences (PN sequences) to solve interconnection problems in VLSI systems. The basic concept is code multiplexing of logic values for the increase of information density in logic networks. The set-valued logic network obtained has the attractive features of high information density, highly parallel structure and extensibility into ultra- higher-valued logic systems.

No.15 Design of a VLSI Prosessor Based on Dual-Rail Current-Mode Multiple-Valued Integrated Circuits
Y.Ito and M. Kameyama
(Tohoku University)
This paper presents a dual-rail current-mode multiple-valued pass gate and its application to a reconfigurable VLSI processor. This pass gate is based on a source-coupled logic circuit with high current-driving capability. The source-coupled MOS integrated circuit is effectively employed for design of the pass gate with high current-driving capability. A high-speed compact quaternary D-latch circuit is also proposed using the pass gates. Moreover, it is made clear that the pass gates are very useful to overcome the communication bottleneck in the reconfigurable VLSI processor.

No.16 Design of Quaternary Sum of Product Operation Systolic Circuit
for Finite Fields using Neuron- MOSFETs
T. Murayama, N. Muranaka and S. Imanishi
(Kansai University)
It is useful that we have sum of product operation circuit for finite fields in linear brock code system. In this paper, we propose quaternary sum of product systolic circuit using neuron-MOSFETs, because it is useful that we have VLSI implementation of the circuit in multiple- valued logic system. It is shown in this paper that the elements of our quaternary circuit decrease in number than the ones of the binary circuit.

No.17 Recognition of Shaded Patterns by using Multiple Valued Input Neuron Model
M. Iizuka D. Sekimoto M. Matsumoto
(Toyo University)
This paper propose a structure of new neuron model. It was already showed that Multiple Valued Logic (MVL) neuron model is superior in certainty to the linear neuron model. MVL neuron model needs a transformation from multiple value to binary value, and we have doubts about its extension. Then we suggest a Multiple Valued Input neuron model and examine its performance. As a result we have dreatly decreased a number of synapse weights of a neural unit.

No.18 Vector Rastor Convertor of Line Draw based on Floating Radix using Redundant Number System
T. Gomi and F. Wakui
(Nihon University)
Picture disposal of printer or display for rastor scan method require to calculate at the rastor data for the vector data accurately. In the figure indication, the straight line is the most fundamental disposal. Therefore we propose an algorithm of line draw baced on floating radix newly. The number of calculation decrease by this algorithm, make variable quantities between start point and end point of vector data the radix, moreover it is possible to use radix-2 signed digit full adder without decoder. Vector rastor converter composed of this algorithm is speedier and compacter than conventional vector rastor converter.