氏名 / Name
稲木 雅人 (いなぎ まさと) / Masato INAGI
所属 / Affiliation
広島市立大学 / Hiroshima City University
大学院 情報科学研究科 / Graduate School of Information Sciences
情報工学専攻 / Department of Computers and Network Engineering
論理回路システム研究室 / Logic Circuit System Lab.
職位 / Job Title
講師 / Lecturer (Assistant Professor)
学位 / Academic Title
東京工業大学博士(工学)(2008) / Ph.D. in Engineering from Tokyo Institute of Technology
専門分野 / Major
VLSI自動設計 / VLSI Design Automation
メール / Mail
inagi"-atmark-"hiroshima-cu.ac.jp
居室 / Location
情報科学部棟 412号室 / Faculty of Information Sciences, room 412
経歴 / Academic background and Career
2000 東京工業大学 工学部 情報工学科 卒業 (梶谷高橋研) 2000 received B.E. in Computer Science from Tokyo Institute of Technology (Kajitani & Takahashi Lab.)
2002 東京工業大学 大学院 理工学研究科 集積システム専攻 修士課程 修了
(梶谷高橋研) 2002 received M.E. in Integrated Systems from Tokyo Institute of Technology (Kajitani & Takahashi Lab.)
2003 ハノーバー大学 マイクロエレクトロニックシステム研究所(12月-3月)
(Pirsch研) 2003 visited Hannover University (Architectures and Systems Group, Institute of Microelectronic Systems)
as an exchange student from Dec. to March
2005 東京工業大学 大学院 理工学研究科 集積システム専攻 博士課程 単位取得退学 (高橋(篤)研) 2005 left Tokyo Institute of Technology (Takahashi Lab.)
2008 東京工業大学 大学院 理工学研究科 集積システム専攻 博士号取得 2008 received Ph.D. from Tokyo Institute of Technology
2005 - 2007 北九州産業学術推進機構 一般研究員 (知的クラスタ) 2005 - 2007 Researcher at Kitakyushu Foundation for the Advancement of Industory, Sciences and Tchnology
2005 - 2008 北九州市立大学 国際環境工学部
特任研究員(梶谷宮下中武高島グループ) 2005 - 2007 Researcher at the University of Kitakyushu (Kajitani & Miyashita & Nakatake & Takashima group)
2008 - 2018 広島市立大学 大学院 情報科学研究科 情報工学専攻 助教
(論理回路システム研究室) 2008 - 2018 Research Associate at Hiroshima City University (Logic Circuit System Lab.)
2018 - 現職 広島市立大学 大学院 情報科学研究科 情報工学専攻 講師
(論理回路システム研究室) 2018 - ---- Lecturer at Hiroshima City University (Logic Circuit System Lab.)
[JP8]
M. Inagi, Y. Nakamura, Y. Takashima, S.Wakabayashi,
"Inter-FPGA Routing for Partially Time-Multiplexing Inter-FPGA Signals on
Multi-FPGA Systems with Various Topologies,"
IEICE Trans. on Fundamentals, Vol. E98-A, No.12, pp.2572-2583, Dec. 2015.
[JP7] Y. Wakaba, S. Wakabayashi, S. Nagayama,
M. Inagi, "An Area
Efficient Regular Expression Matching Engine Using Partial
Reconfiguration for Quick Pattern Updating," IPSJ Transactions on
System LSI Design Methodology, Vol. 7, pp.110-118, August 2014.
[JP6] 若葉陽一, 若林真一, 稲木
雅人, 永山忍, "シストリックアルゴリズムとNFAに基づくパターン非依存正規表現マッチングハードウェア,"
電子情報通信学会論文誌D, Vol.J96-D, No.10, pp.2139-2149, Oct. 2013.
(Y. Wakaba, S. Wakabayashi, M.
Inagi, S. Nagayama, "Pattern-Independent Regular
Expression Matching Hardware Based on Systolic Algorithm and NFA,"
IEICE Trans. on Information and Systems, Vol.J96-D, No.10,
pp.2139-2149, Oct. 2013. (in Japanese) )
[JP5] M. Nakamura, M.
Inagi,
K. Tanigawa, T. Hironaka, M. Sato, T. Ishiguro, "A Physical Design
Method for a New Memory-Based Reconfigurable Architecture without
Switch Blocks," IEICE Trans. on Information and Systems, Vol.E95-D,
No.2, pp.324-334, February 2012.
[JP4] M.
Inagi,
Y. Takashima, Y. Nakamura, "Globally Optimal
Time-multiplexing of Inter-FPGA Connections for Multi-FPGA
Prototyping Systems," IPSJ Trans. on System LSI Design Methodology,
Vol.3, pp.81-90, February 2010.
[JP3] M.
Inagi,
Y. Takashima, Y. Nakamura, and A. Takahashi, "Optimal
Time-multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA
Prototyping Systems," IEICE Trans. on Fundamentals, Vol.E91-A, No.12,
pp.3539-3547, December 2008.
[JP2] M.
Inagi,
Y. Takashima, Y. Nakamura, and Y. Kajitani, "A Performance-driven
Bipartitioning Method for Multi-FPGA Implementation
with Time-multiplexed I/Os," IEICE Trans. on Fundamentals, Vol.E90-A,
No.5, pp.924-931, May 2007.
[JP1] K. R. Azegami, M.
Inagi, A. Takahashi, and Y. Kajitani, "An Improvement of
Network-Flow Based Multi-Way Circuit Partitioning
Algorithm," IEICE Trans. on Fundamentals, Vol.E85-A, No.3, pp.655-663,
March 2002.
国際会議等 (International Conferences)
[ICP27] Yuri Itotani, Shin'ichi Wakabayashi, Shinobu. Nagayama, Masato Inagi, "An Approximate Nearest Neighbor Search Algorithm Using Distance-based Hashing," Proc. the 28th International Conference on Database and Expart Systems Applications (DEXA2018), pp.203-2013, Sep. 2018. (Regensburg, Germany)
[ICP26] Gaku Kataoka, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama, "Novel Feature Vectors Considering Distances between Wires for Lithography Hotspot Detection," Proc. the 21st Euromicro conference on Digital Sytem Design (DSD2018), pp.85-90, Aug. 2018. (Prague, Czech)
[ICP25] T. Ito, Y. Itotani, S. Wakabayashi, S. Nagayama, M. Inagi, "An FPGA-based Nearest Neighbor Search Engine Using Distance-based Hashing for High-Dimensional Data," Proc. the 21st Workshop on Synthesis And System Integration of Mixed Information
Technology (SASIMI2018), March 2018. (Matsue, Japan)
[ICP24] B. Xue, S. Nagayama, M. Inagi, S. Wakabayashi, "A Programmable Architecture Based on Vectorized EVBDDs for Network Intrusion Detection Using Random Forests," Proc. the 2017 International Symposium on Nonlinear Theory and Its Applications (NOLTA2017), Dec. 2017. (Cancun, Mexco)
[ICP23] S. Tamagawa, M. Inagi, S. Nagayama, S. Wakabayashi, "Table Reference-Based Accleleration of a Lithography Hotspot Detection Method Based on Approximate String Search," Proc. the tenth international conference on advances in Circuits, Electronics and micro-electroNICS (IARIA CENICS2017), pp.8-14, Sep. 2016. (Rome, Italy)
[ICP22] Y. Arai, S. Wakabayashi, S. Nagayama, M. Inagi, "An Efficient FPGA Implementation of Maharanobis Distance-Based Outlier Detection for Streaming Data," Proc. international conference on Field Programmable Technology (IEEE FPT2016), pp.251-256, Dec. 2016. (Xi'an, China)
[ICP21] T. Hashimoto, S. Wakabayashi, S. Nagayama, M. Inagi, R. Koishi, H. Takaguchi, "A High-Speed Programmable Network Intrusion Detection System Based on a Multi-Byte Transition NFA," Proc. the ninth international conference on advances in Circuits, Electronics and micro-electroNICS (IARIA CENICS2016), pp.45-51, July 2016. (Nice, France)
[ICP20] S. Tamagawa, R. Fujimoto, M. Inagi, S. Nagayama, S. Wakabayashi, "A Hotspot Detection Method Based on Approximate String Search," Proc. the ninth international conference on advances in Circuits, Electronics and micro-electroNICS (IARIA CENICS2016), pp.6-12, July 2016. (Nice, France)
[ICP19] H. Nishiyama, M. Inagi, S. Wakabayashi, S. Nagayama, K. Inoue, M. Kaneko, "An ILP-based Optimal Circuit Mapping Method for PLDs," Proc. the 21st Reconfigurable Architecture Workshop (RAW2014/IEEE IPDPSW2014), pp.251-256, May 2014. (Phoenix, USA)
[ICP18] H. Takaguchi, Y. Wakaba, S. Wakabayashi, S. Nagayama, M.
Inagi, "An NFA-Based Programmable Regular Expression
Matching Engine Highly Suitable for FPGA Implementation," In Proc. the
18th Workshop on Synthesis And System Integration of Mixed Information
Technology (SASIMI2013),
pp.231-236, Oct.
2013. (Sapporo, Japan)
[ICP17] Y. Shintani, M.
Inagi, S. Nagayama, S. Wakabayashi,
"A Multithreaded Parallel Global Routing Method with Overlapped Routing
Regions," In Proc. the 2013 Euromicro Conference on Digital System
Design (DSD2013), pp.591-597, Sept.
2013. (Santander, Spain)
[ICP16] Y. Wakaba, S. Nagayama, S. Wakabayashi, M.
Inagi, "A Flexible and Compact Regular Expression Matching
Engine Using Partial Reconfiguration for FPGA," In Proc. the 2013
Euromicro Conference on Digital System Design (DSD2013), pp.293-296,
Sept.
2013. (Santander, Spain)
[ICP15] Y. Tanihara, M.
Inagi, S. Wakabayashi, S. Nagayama,
"GPGPU Implementation of Tabu Search for the Quadratic Assignment
Problem," In Proc. the 27th Int. Tech. Conf. on Circuits/Systems,
Computers and
Communications (ITC-CSCC2012), July
2012. (Sapporo, Japan)
[ICP14] Y. Utan, M.
Inagi, S. Wakabayashi, S. Nagayama,
"A GPGPU Implementation of Approximate String Matching with Regular
Expression Operators and Comparison with Its FPGA Implementation," In
Proc. the 2012 Int. Conf. on Parallel and Distributed Processing
Techniques and Applications (PDPTA2012),
pp.644-649, July
2012. (Las Vegas, USA)
[ICP13] Y. Wakaba, M.
Inagi, S. Wakabayashi, "A Practical FPGA Implementation of
Regular Expression Matching with Look-ahead Assertion," In Proc. the
2012 Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA2012),
pp.105-110, July
2012. (Las Vegas, USA)
[ICP12] Y. Wakaba, S. Nagayama, M.
Inagi, S. Wakabayashi, "A Matching Method for Look-ahead
Assertion on Pattern Independent Regular Expression Matching Engine,"
In Proc. the 17th Workshop on Synthesis And System Integration of Mixed
Information Technology (SASIMI2012),
pp.361-366, March
2012. (Beppu, Japan)
[ICP11] M.
Inagi, M. Nakamura,
T. Hironaka, T. Ishiguro, "Net-based Move in SA-based Placement for a
Switch-block-free Reconfigurable Device," In Proc. the 17th Workshop on
Synthesis And System Integration of Mixed Information Technology
(SASIMI2012),
pp.239-240, March
2012. (Beppu, Japan)
[ICP10] M. Nakamura, M.
Inagi,
K. Tanigawa, T. Hironaka, M. Sato, T. Ishiguro, "EDA Environment for
Evaluating a New Switch-Block-Free Reconfigurable Architecture," In
Proc. the 2011 Int. Conf. on ReConFigurable Computing and FPGAs
(ReConFig2011),
pp.448-454, Nov.
2011. (Cancun, Mexco)
[ICP9] Y. Wakaba, M.
Inagi,
S. Wakabayashi, S. Nagayama, "An Efficient Hardware Matching Engine for
Regular Expression with Nested Kleene Operators," In Proc. the 21st
Int. Conf. on Field Programmable Logic and applications (FPL2011),
pp.157-161, Sept.
2011. (Ceret, Greece)
[ICP8] Y. Wakaba, M.
Inagi,
S. Wakabayashi, S. Nagayama, "An Extension of Systolic Regular
Expression Matching Hardware for Handling Iteration of Strings Using
Quantifiers," In Proc. the 16th Workshop on Synthesis and System
Integration of Mixed
Information technologies (SASIMI2010),
pp.412-417, Oct.
2010. (Taipei, Taiwan)
[ICP7] M.
Inagi,
Y. Takashima, Y. Nakamura, "Globally Optimal
Time-multiplexing in inter-FPGA Connections for Accelerating
Multi-FPGA Systems," In Proc. Int. Conf. on Field
Programmable Logic and Applications 2009 (FPL2009), pp.212-217, Sep.
2009. (Prague, Czech)
[ICP6] M.
Inagi,
Y. Takashima, Y. Nakamura,
"Evaluation of Introducing Multiple Time-multiplexing Degrees to
Inter-FPGA Connections
on Multi-FPGA Systems,"
In Proc. Int. Technical Conf. on Circuit/Systems Computers and
Communications 2009 (ITC-CSCC2009), pp.1032-1035,
July 2009. (Jeju, Korea)
[ICP5] Y. Wakamoto, S. Nagayama, M.
Inagi,
S. Wakabayashi,
"Design and FPGA Implementation of Efficient Discrete Function
Generators Using Piecewise Polynomial Approximations,"
In Proc. Int. Technical Conf. on Circuit/Systems Computers and
Communications 2009 (ITC-CSCC2009), pp.1016-1019,
July 2009. (Jeju, Korea)
[ICP4] T. Sato, M.
Inagi,
S. Nagayama, S. Wakabayashi,
"A Parallel Simulated Annealing for LSI Floorplanning Running on
Multi-core Processors,"
In Proc. Int. Technical Conf. on Circuit/Systems Computers and
Communications 2009 (ITC-CSCC2009), pp.851-854,
July 2009. (Jeju, Korea)
[ICP3] M.
Inagi,
Y. Takashima, Y. Nakamura, and A. Takahashi,
"ILP-Based Optimization of Time-Multiplexed I/O Assignment
for Multi-FPGA Systems,"
In Proc. IEEE Int. Symposium on Circuit and Systems 2008 (ISCAS2008),
pp.1800-1803,
June 2008. (Seatle, USA)
[ICP2] M.
Inagi,
Y. Takashima, Y. Nakamura, and Y. Kajitani,
"A Performance-driven Circuit Bipartitioning Algorithm for Multi-FPGA
Implementation with Time-multiplexed I/Os," In Proc. IEEE Int.
Conference on Field Programmable Technology 2006 (ICFPT2006),
pp.361-364, December 2006. (Bangkok, Tailand)
[ICP1] M.
Inagi,
and A. Takahashi,
"Network-Flow Based Delay Aware Partitioning Algorithm,"
In Proc. the 13th Workshop on Synthesis and System Integration of Mixed
Information technologies (SASIMI2006), pp.417-422, April 2006. (Nagoya, Japan)
M.
Inagi, T. Sato, S. Nagayama, S. Wakabayashi,
"LSI Floorplanning Based on Parallel Simulated Annealing for Muticore
Processors,"
In Proc. DA Symposium 2009 (ISPJ Symposium Series Vol.2009, No.7,)
pp.61-66, August 2009.